1. Technical Field
This disclosure relates to clock tree synthesis during electronic circuit design. More specifically, this disclosure relates to automatic clock tree routing rule generation.
2. Related Art
Advances in semiconductor technology presently make it possible to integrate hundreds of millions of transistors onto a single semiconductor chip. This dramatic increase in semiconductor integration densities has made it considerably more challenging to design circuits.
Clock tree synthesis (CTS) and routing are two important operations in electronic design automation (EDA). CTS refers to the process of creating a clock distribution network for distributing a clock signal to a set of sequential circuit elements in a circuit design. Routing a circuit design (which includes routing one or more clock trees in the circuit design) involves determining routes for metal wires which electrically connect circuit elements to produce routed circuits that perform desired functions. The quality of the routed clock trees that are generated by a router can have a significant impact on downstream stages in the EDA design flow.